The EEPROM (Electrically Erasable Programmable Read Only Memory), which corresponds to one form of a nonvolatile memory, may generally be classified into two types according the number of gates used. Namely, the EEPROM may be classified into a one-layer gate type nonvolatile memory and a two-layer gate type nonvolatile memory. For example, Japanese Laid-Open Patent Publication No. 6-85275 and Japanese Translated International Patent Application Publication No. 8-506693 disclose technologies relating to the one-layer gate type nonvolatile memory, and Japanese Examined Patent Publication No. 4-80544 discloses technology relating to the two-layer type nonvolatile memory.
FIG. 1 is a plan view of a one-layer gate type nonvolatile memory. The nonvolatile memory shown in FIG. 1 includes a p-type semiconductor substrate (p-substrate) 101, n-type diffusion layers 103, 105, 107, and a control gate 109. It is noted that a space is arranged between the n-type diffusion layers 103 and 105, and a space is arranged between the n-type diffusion layers 105 and 107.
A selection gate 111 made of a polysilicon film is arranged via a gate oxide film (not shown) at a region of the p-substrate 101 including the region between the n-type diffusion layers 103 and 105 to overlap with portions of the n-type diffusion layers 103 and 105. A floating gate 113 made of a polysilicon film is arranged via a silicon oxide film (not shown) to extend over a region of the p-substrate 101 including the region between the n-type diffusion layers 105 and 107 and the control gate 109. It is noted that the floating gate 113 is arranged to partially overlap with portions of the n-type diffusion layers 105 and 107 via a memory gate oxide film.
Upon performing a write operation on this one-layer gate type nonvolatile memory, namely, upon implanting electrons into the floating gate 113, the n-type diffusion layer 103 is set to 0 V, the n-type diffusion layer 107 is set to a predetermined potential Vpp, and the predetermined potential Vpp is applied to the control gate 109 and the selection gate 111. In this way, a transistor realized by the n-type diffusion layers 103, 105, and the selection gate 111 may be turned on, and electrons may be implanted from the n-type diffusion layer 105 via the memory gate oxide film into the floating gate 113.
Upon performing an erase operation on this one-layer gate type nonvolatile memory, namely, upon discharging electrons from the floating gate 113, the control gate 109 is set to 0 V, the n-type diffusion layer 107 is opened, and the predetermined potential Vpp is applied to the n-type diffusion layer 103 and the selection gate 111. In this way, the transistor realized by the n-type diffusion layers 103, 105, and the selection gate 111 may be turned on, and electrons implanted in the floating gate 113 may be withdrawn via the memory gate oxide film into the n-type diffusion layer 105 by a tunneling effect.
FIG. 2 is a cross-sectional view of a two-layer gate type nonvolatile memory. The nonvolatile memory shown in FIG. 2 includes a p-substrate 101 and n-type diffusion layers 117 and 119 that are spaced apart from one another. A floating gate 123 made of a polysilicon film is arranged via a memory gate oxide film 121 at a region of the p-substrate 101 including the region between the n-type diffusion layers 117 and 119 to partially overlap with portions of the n-type diffusion layers 117 and 119. A control gate 127 made of a polysilicon film is arranged on the floating gate 123 via a silicon oxide film 125.
Upon performing a write operation on this two-layer gate type nonvolatile memory, namely, upon implanting electrons into the floating gate 123, the n-type diffusion layer 119 is set to 0 V, the n-type diffusion layer 117 is set to a predetermined potential Vpp, and the predetermined potential Vpp is applied to the control gates 127. In this way, electrons may be implanted from the n-type diffusion layer 119 via the memory gate oxide film into the floating gate 123.
Upon performing an erase operation on this two-layer gate type nonvolatile memory, namely, upon discharging electrons from the floating gate 123, the control gate 127 is set to 0 V, the n-type diffusion layer 117 is opened, and a predetermined potential Vpp is applied to the n-type diffusion layer 119. In this way, electrons implanted into the floating gate 123 may be withdrawn via the memory gate oxide film 121 into the n-type diffusion layer 119.
Japanese Laid-Open Patent Publication No. 2003-168747 and Japanese Laid-Open Patent Publication No. 2004-31920 disclose technologies relating to a nonvolatile memory cell that does not include a control gate.
FIGS. 3A and 3B are diagrams illustrating a nonvolatile memory that does not include a control gate, FIG. 3A being a plan view and FIG. 3B being a cross-sectional view of such a nonvolatile memory. It is noted that in these drawings, components that have identical functions to those shown in FIGS. 1 and 2 are given the same numerical references.
The nonvolatile memory shown in FIGS. 3A and 3B include a p-substrate 101, and n-type diffusion layers 103, 105, and 107. It is noted that a space is arranged between the n-type diffusion layers 103 and 105, and a space is arranged between the n-type diffusion layers 105 and 107.
A selection gate 111 made of a polysilicon film is arranged via a gate oxide film 129 on a region of the p-substrate 101 including the region between the n-type diffusion layers 103 and 105 to partially overlap with portions of the n-type diffusion layers 103 and 105. A floating gate 123 made of a polysilicon film is arranged via a memory gate oxide film 121 at a region of the p-substrate 101 including the region between the n-type diffusion layers 105 and 107 to realize a memory transistor. The floating transistor 123 is arranged to partially overlap with portions of the n-type diffusion layers 105 and 107 via the memory gate oxide film 121.
Upon performing an erase operation on this nonvolatile memory, namely, upon discharging electrons from the floating gate 123, for example, ultra violet rays may be irradiated on the floating transistor 123 so that the floating transistor 123 may be initialized to a zero-charge state.
In this case, the n-type diffusion layer 103 is set to 0 V, the n-type diffusion layer 107 and the selection gate 111 are set to a predetermined potential Vpp such as 7 V, for example. In this way, a selection transistor realized by the n-type diffusion layers 103, 105, and the selection gate 111 may be turned on, and electrons implanted in the floating gate 123 may be withdrawn via the memory gate oxide film 121 into the n-type diffusion layer 105 by a tunneling effect. In this example, the n-type diffusion layer 103 and the floating gate 123 have to adequately overlap with each other. Accordingly, an embedded n-type diffusion layer is at the n-type diffusion layer 105 side arranged below the floating gate 123 as is described in Japanese Laid-Open Patent Publication No. 2003-168747.
Upon performing a write operation on this nonvolatile memory, namely, upon implanting electrons into the floating gate 123, the n-type diffusion layer 107 is set to 0 V, a predetermined potential Vpp such as 4.5 V is applied to the n-type diffusion layer 103, and the selection gate ill is set to a predetermined voltage Von such as 2 V. In this way, the selection transistor realized by the n-type diffusion layers 103, 105, and the selection gate 111 may be set on, and electrons may be implanted from the n-type diffusion layer 105 via the memory gate oxide film 121 into the floating gate 123. In this case, the embedded type n-type diffusion layer has to be present as in the case of performing the erase operation.
Also, it is noted that Japanese Laid-Open Patent Publication No. 2004-31920 discloses arranging a gate oxide film of a MOS (Metal Oxide of Silicon) transistor realizing a peripheral circuit such as a logic circuit to have the same thickness as a gate oxide film of a selection transistor and a gate oxide film of a memory transistor.
When the gate oxide films of a memory transistor that does not include a control gate, a selection transistor, and a peripheral circuit transistor are arranged to have the same thickness as is taught in Japanese Laid-Open Patent Publication No. 2004-31920, when the gate oxide film is arranged to have a thickness at a sub half level of 7.5 nm, for example, the memory gate oxide film of the memory transistor also has a thickness of 7.5 mm. In this case, it has been found through experiment by the inventor of the present invention that a predetermined potential Vpp of approximately 6-7 V or greater is required in order to obtain good writing characteristics.
However, in this case, a voltage of 6-7 V or greater, for example, has to be applied to the peripheral circuit transistor that is configured to apply the predetermined potential Vpp to the memory upon performing a write operation on the memory transistor. This means that an electric field reaching up to approximately 10 MV/cm is applied to the 7.5 nm-thick gate oxide film of the peripheral circuit transistor (referred to as ‘peripheral circuit gate oxide film’ hereinafter), and thereby, the peripheral circuit gate oxide film may be vulnerable to damage and the yield and reliability of the corresponding semiconductor device may be degraded. Also, according to findings of the inventor of the present invention, the snapback voltage of a NMOS transistor (N channel MOS transistor) having a 7.5 nm-thick gate oxide film is around 6-7 V, which is substantially equal to the predetermined potential Vpp, and thereby, the peripheral circuit may be vulnerable to damage when a write operation is performed on the memory transistor, and the yield and reliability of the corresponding semiconductor device may be degraded from this aspect as well.
In order to prevent such problems, the gate oxide film thickness of the memory transistor, the selection transistor, and the peripheral circuit transistor may be set to half level of approximately 13.5 nm, for example. However, when the gate oxide film thickness is increased, the write voltage Vpp also has to be increased so that this does not solve the problems arising in the case where the gate oxide film thickness is set to sub half level. When the thickness of the gate oxide film is arranged to be approximately 13.5 nm and the write voltage Vpp is set to approximately 6-7 V, although damage to the peripheral circuit gate oxide film may be prevented, the memory gate oxide film of the memory transistor is also arranged to be 13.5 nm so that good writing characteristics may not be obtained.
Also, the inventor of the present invention has tested and evaluated the semiconductor device disclosed in Japanese Laid-Open Patent Publication No. 2004-31920 including the memory transistor without a control gate, the selection transistor, and the peripheral circuit transistor, and has found that sufficient charge retaining characteristics cannot be obtained in this semiconductor device primarily owing to high impurity concentration within the polysilicon of the floating gate.